发明名称 MULTIPROCESSOR BUS CONTROL SYSTEM
摘要 PURPOSE:To attain a communication even when a trouble is generated in one unit of a system bus by providing a bidirectional buffer connected in parallel to a shared RAM on the way of a system. CONSTITUTION:In an ordinary operation, unit groups connected to the system bus and unit groups connected to the system bus 2 independently and exclusively have the system bus to control. The delivery between the bus 1 and the bus 2 is carried out through the shared RAM3. However, for instance, when the trouble is generated in the CPU21, the contents of a RAM22 cannot be written in the RAM3 by the CPU21. In such a case, the CPU11 validates the bidirectional buffer 4 to make access directly to the RAM22, thereby, the communication can be maintained to the unit except the CPU21.
申请公布号 JPS63158660(A) 申请公布日期 1988.07.01
申请号 JP19860307285 申请日期 1986.12.23
申请人 FANUC LTD 发明人 KATAOKA MINORU;MIURA KAZUHIKO
分类号 G06F15/16;G06F15/167;G06F15/177 主分类号 G06F15/16
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