发明名称 CACHE MEMORY
摘要 PURPOSE:To speed up an access time by comparing the contents of a first register with the second register, and selecting the output of a block red buffer when they coincide with each other. CONSTITUTION:A read address from a CPU 200 is set in a first register 3 by a read start signal (b). By resetting the present block read address to the second register 4 from the register 3 by an answer signal from a memory 300, the successive same block read address is compared by a comparator 5. If they coincide, the data of the block read buffer 8 can be transferred to the CPU 200 without accessing a cache memory 100. Accordingly, the access time seen by the CPU 200 can be speeded up, without being aware of the error of the memory 100, etc.
申请公布号 JPS63158648(A) 申请公布日期 1988.07.01
申请号 JP19860306753 申请日期 1986.12.23
申请人 NEC CORP 发明人 MAEDA KENICHI
分类号 G06F12/08 主分类号 G06F12/08
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