| 摘要 |
PURPOSE:To prevent a latch-up phenomenon completely, and to reduce an element area without deteriorating characteristics by constituting a complementary type semiconductor device of N channel and P channel MIS transistors arranged in three dimensions by using three holes bored in the main surface of a semiconductor substrate. CONSTITUTION:A hole 23 is formed into a P-type semiconductor substrate 21, penetrating a source region 22 in an N channel MIS transistor in the surface of the P-type semiconductor substrate 21, and a drain region 24 in the N channel MIS transistor is shaped onto the base of the hole 23. A gate insulating film 25 in the N channel MIS transistor, a gate electrode 26, a gate insulating film 27 in a P channel MIS transistor, the P channel MIS transistor 28, an inter-layer insulating film 29, and an output electrode 30 are laminated along the side wall of the hole 23 in succession, and a drain region 31 in the P channel MIS transistor 28 shaped near the base of the hole 23 is connected to the drain region 24 by the output electrode 30. A source region 32 in the P channel MIS transistor 28 is formed near the surface of the hole 23. |
