| 摘要 |
PURPOSE:To detect the shortage or surplus of the pulse in bit flow on real time, by using a logical means for judging whether the number of pulses present within the one round period of a reference pulse are regular. CONSTITUTION:A clock edge selection circuit 46 forms data flow 49 to be tested and a reference cell 55 on the basis of the reference clock inputs J-L based on the parameter determined by a user and clock pulses are applied to a flip-flop 54 through the first and second delay circuits 48, 52. The flip-flop 54 judges whether a pulse 57 to be tested is present in the pulses 59 of a reference pulse or a plurality of pulses are present in the same cell and outputs the output pulse corresponding thereto to a line 61. A sequencer/counter 44 responds to the output of the flip-flop 54 and outputs a signal indicating the shortage of the pulse to a line 41 when there is no pulse in the aforementioned cell and outputs a signal indicting the presence of excessive pulses to said line 41 when two pulses are present in the cell to trigger an oscilloscope.
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