| 摘要 |
PURPOSE:To attain decoding at high speed even if the bit length of an information symbol becomes longer by searching the tolerance of the information symbol in a bit unit and sequentially estimating the bit expression of the information symbol. CONSTITUTION:A reception signal is inputted to a register 112 and a state holding circuit 102 through an input buffer 111. While a sequential decoding control circuit 115 judges that a past estimation is correct, it shifts the content of the state holding circuit 102 and outputs it to a buffer 114. When said circuit 115 judges that the estimation is wrong and returns the state of a decoder to that of the past, it takes out a bit inputted to the buffer 114, holds it to the state holding circuit 102 and simultaneously holds the reception signal inputted to a buffer 113 in the past in the register 112. The estimated value of the information bit, namely, a decoded result is accumulated in the buffer 114 and the decoded result is outputted from an output terminal 104. |
