| 摘要 |
PURPOSE:To boost the latch up voltage by a method wherein the first n<->base is provided on a p<+>layer a barrier layer in wide forbidden band width and second base are laminated on the first n<->base p bases and source layers are provided on the surface and gate electrodes are provided on the p bases between the p bases and n type source layers through the intermediary of insulating layers. CONSTITUTION:A hole passage preventing n layer 2 is laminated on a hole injection source P<+>layer 1. The n layer 2 is composed of the first n<->base 3 and a barrier 4. The barrier 4 comprising SixC1-x etc., is doped into n type to flatten the n base and a conductive band Ec while preventing hole from tunneling. Next, the second n bases 5 as substantial drains are laminated to provide gate electrodes 11 on p bases 7 between p wells 6, p bases 7, n<+>sources 8, n base 5 and the N+sources 8 on the surface through the intermediary of insulating film 10 and then a source electrode 15 is formed through the intermediary of another insulating films 14. In such a constitution, minor carriers are injected from the p<+>layer 1 the n<->layer 3 to reduce ON resistance of FET. Furthermore, the minor carriers are prevented from passing through by the barrier 4 to be almost extinguished by recoupling not to reach the p base layers 7 preventing the latch up from occurong. |
