VERTICAL TYPE SEMICONDUCTOR MEMORY CELL AND MANUFACTURE OF THE SAME

摘要

A vertical DRAM structure comprising a VMOS transistor and trench capacitor in combination wherein the access transistors are in a V-groove and the capacitors are in two vertical layers. The structure has only a single level of polysilicon and has no contacts. The memory cell circuit is a one-device memory cell, having a single access transistor with its gate (40) connected to a word line (WL), its drain (30) connected to a bit line (BL), and its source (22) connected to a storage capacitor. More particularly, the storage capacitance node (16) is connected to the source (22) of the V-groove access device through a conducting bridge (e.g. 18). An epitaxial layer (26) is grown over a combination of single crystalline material and oxide. Polycrystalline regions in the silicon substrate have an oxide covering. In an alternate version, a single crystal epitaxial layer is disposed over regions consisting of both single crystal and poly crystal Si or polycrystalline material on top of single crystalline material is converted into single crystalline material.