| 摘要 |
PURPOSE:To easily attain synchronous detection with reduced synchronous action by calculating a remainder of a code polynominal and a generation polynominal in which a code length K bit is taken out from information is set to a coefficient, and controlling the replacement of channels. CONSTITUTION:A multiplier 209 generates the cyclic code of the code length K bit generated from the previously decided generation polynominal. The information bit on the cyclic code is inserted into parallel transmission information in frame synchronous pattern insertion circuits 2041-2044. Output signals outputted from the frame synchronous pattern insertion circuits 2041-2044 are converted into serial information in a parallel-series conversion circuit 205 and are outputted. |
