| 摘要 |
PURPOSE:To omit the time needed for decoding the detected data and to attain the processing at a high speed with a normalized circuit, by using a bidirectional shifter of a matrix structure. CONSTITUTION:When the detected data with which a terminal 21a is set at '1' among those terminals 21a-21e of a shifter 12 is supplied, the transmission gates. T1, T3, T6 and T10 conduct. Then the bits of mantissa parts 2<1>-2<2> supplied to terminals 20a-20d are shifted to the right (the lower direction) and delivered through terminals 32a-32d in the form of the bits of mantissa parts 2<0>-2<3> respectively. When the detected data with which the terminal 21c is set at '1' is supplied, the transmission gates T4, T8 and T13 and an FETQ3 conduct and the bits of mantissa parts 2<-1>-2<-3> supplied to terminals 20c-20e are shifted to the left (the upper direction). Then these bits are outputted as the bits of mantissa parts 2<0>-2<-2> through terminals 32a-32c. Then the bit of a mantissa part 2<-3> supplied from the terminal 32d is set at '0'. |
