| 摘要 |
<p>PURPOSE:To apply arithmetic processing to image data at high speed and to attain a general-purpose data processing system having a high degree of freedom, by connecting in parallel plural processors of a high-speed image parallel pipeline processing system and actuating these processors with the same system clock. CONSTITUTION:The processors 10R, 10G and 10B are connected in parallel to a control part 11 which produces control timing for an entire process via connection lines 121, 122 and 123. The part 11 produces a system clock, and vertical and horizontal synchronizing signals which are synchronous with said system clock and supplies these clock and signals to a TV camera or a monitor TV receiver connected to the outside. In this case, network circuits 13R, 13G and 13B form combinations of inputs/outputs of processors 14R, 14G and 14B. The image data received from the TV camera are processed synchronously with a system clock and displayed on the monitor TV receiver. In such constitution, a network circuit can be extended just with a simple connection to a plug.</p> |
