发明名称 SYNCHRONIZING SIGNAL SAMPLING CIRCUIT
摘要 PURPOSE:To sample a synchronizing signal with high accuracy even from a video signal of adverse quality by applying pulse clamp except the 9-line vertical period where distortion is often caused easily thereby correcting leakage current caused during the 9-line vertical period. CONSTITUTION:A high frequency component is eliminated from an input video signal at first by an LPF, the result is fed to an amplifier 1, where the level is amplified and a built-in limiter eliminates the signal of the picture part above the slice level. A DC bias control circuit 2 to ensure the operation of the amplifier 1 is provided. The pedestal part in the output of the amplifier 1 is fixed in terms of DC to ensure the elimination of the signal of the picture part. The pedestal part of the output of the amplifier 1 is clamped to a ground level by using a clamp FETQ2. In such a case, since the synchronizing signal itself is often distorted during the 9-line vertical period, a leakage current correcting circuit 3 is provided to inhibit the DC bias control and clamping operation and to suppress the fluctuation of the DC level during this period.
申请公布号 JPS63157571(A) 申请公布日期 1988.06.30
申请号 JP19860305877 申请日期 1986.12.22
申请人 SONY CORP 发明人 NARITA ATSUO
分类号 H04N5/08;H04N5/18 主分类号 H04N5/08
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