发明名称 FRAME SYNCHRONIZING SYSTEM
摘要 PURPOSE:To easily confirm step out, by performing modulation after code conversion is applied on a prescribed modulation unit on which a dummy bit is added, to discriminate the modulation unit on which the dummy bit is added out of plural multi-dimensional modulation units sandwiched between adjacent frame signals. CONSTITUTION:In step S1, a transmission data is made into a random form, and after that, the plural modulated shares of transmission data are accumulated synchronously with a frame signal, and after the dummy bit is added on and a prescribed time adjustment is performed, the code conversion is applied on a prescribed modulation unit in a frame unit in step S3. Thus, the data on which the code conversion is applied in step S3 is multi-dimensional-modulated in step S4, and it is transferred to a reception side in step 55. At the reception side, the said signal, after being multi-dimensional-demodulated, is code converted, and is taken out as a reception data.
申请公布号 JPS63156450(A) 申请公布日期 1988.06.29
申请号 JP19860304555 申请日期 1986.12.19
申请人 FUJITSU LTD 发明人 KAKO TAKASHI;MURATA HIROYASU;SETO CHIAKI
分类号 H04J3/06;H04L7/00;H04L7/08;H04L27/22 主分类号 H04J3/06
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