发明名称 METHOD FOR PREVENTING PARASITIC EFFECT OF INTEGRATED CIRCUIT
摘要 PURPOSE:To avoid the influence of a parasitic effect upon other elements by a method wherein an optional current is applied to an isolation region corresponding to the transition of the potential of an active element from the substrate potential to a lower potential. CONSTITUTION:When a transistor Tr1 is provided as an active element, together with an epitaxial layer 2 as 1st conductive region, an epitaxial layer 8 is formed between the transistor Tr1 and the forming region of the other element as 2nd conductive region with the same conductivity type. An opposite conductivity type isolation region 4 is provided around the epitaxial layer 2 for isolation. when the potential of the epitaxial layer 2 becomes lower than the potential of a substrate 6, in accordance with the detection of the potential Vn by a potential detector 22, a current I is applied to the isolation region 4 surrounding the transistor TR1 corresponding to the generation of a negative potential. Therefore, a voltage drop is induced with the potential at the point Q of the current application as a peak so that the area required for providing the epitaxial layer 8 is reduced to a partial area where the influence upon an adjacent transistor Tr2 can be avoided. Therefore, a parasitic effect is intensified locally and the influence upon the other parts can be suppressed.
申请公布号 JPS63155757(A) 申请公布日期 1988.06.28
申请号 JP19860303192 申请日期 1986.12.19
申请人 ROHM CO LTD 发明人 NAKAI MASAKI;ASAI KATSUO
分类号 H01L29/73;H01L21/331;H01L21/761;H01L27/02;H01L27/06 主分类号 H01L29/73
代理机构 代理人
主权项
地址