| 摘要 |
PURPOSE:To reduce a limit to an address skew, and to give a degree of freedom to an applied timing of an address signal, by always delaying a timing of access by a second circuit, by the time required for refreshing irrespective of an operation of a first circuit. CONSTITUTION:Access by the second access circuit 3, and usual address access from the outside are always executed by being delayed by the time required for refreshing a memory cell from the time point of an address variation of an address signal ADD from the outside or a level variation of a clock signal CE irrespective of a refreshing access operation by the first access circuit 2. That is to say, a sufficiently long time is secured from the time point of the address variation to the actual access, therefore, a limit to an address skew is reduced. Also, it is unnecessary to apply the address signal ADD by depending on an applied timing of the clock signal CE, therefore, the degree of freedom can be given to an applied timing of the address signal.
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