发明名称 PLL SYNCHRONIZATION DETECTING CIRCUIT
摘要 PURPOSE:To suppress influence due to disturbance such as noise, etc., and to obtain a stable detecting characteristic at the time of inputting a weak electric field signal or an overmodulation signal, by increasing a difference between a mean potential and a reference potential at the time of locking and unlocking a loop circuit. CONSTITUTION:A video intermediate frequency signal is supplied to a first input of each of a video detector 1 and a phase detector 2, and the detector 2 constitutes a PLL circuit with a loop filter 3, a voltage controlled oscillator 4 and a phase shifter 5. And when a PLL signal is unlocked, the detector 1 outputs a video signal OUT. The signal OUT, the lower side of which being clipped by a clipping circuit 10, becomes a clip waveform (a), and its mean potential VAV is set higher than the mean potential of the signal OUT. Therefore, a potential difference between the mean potential of the signal OUT outputted from the detector 1 at the time of locking the PLL signal and the clip waveform is expanded, thereby, a loop filter switching characteristic can be stabilized.
申请公布号 JPS63153974(A) 申请公布日期 1988.06.27
申请号 JP19860299988 申请日期 1986.12.18
申请人 TOSHIBA CORP 发明人 NAKAGAWARA TOMOMASA;SAJI TOMOKI
分类号 H04N5/455 主分类号 H04N5/455
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