| 摘要 |
PURPOSE:To lower the operating frequency of a parity counter circuit, by performing parity count by using signals in which the input date of an nB1P data string is divided into m-systems. CONSTITUTION:An S/P conversion circuit 1 generates output signals (b) and (c) that the input data (a) is divided into two systems, and sets speed at 1/2 that of the input data (a). A signal (c) is delayed by one bit at a one bit delay circuit 2, and either the signal (c) or a delayed signal (c') becomes the output signal (c'') of a selection circuit 3. The signals (b) and (c'') become an output signal (d) via an exclusive OR gate 4. A 4B1 P parity counter circuit 5, after being reset, finds a parity bit, and holds the parity bit at a holding circuit 6, and generates holding outputs (g) and (f). An exclusive OR gate 7 generates a signal (h) from the signals (g) and (f) as the parity bit, and parity count can be obtained from the signals (h) and (g).
|
