| 摘要 |
PURPOSE:To obtain a synchronizing signal with constant pulse width, by detecting the pulse width of the synchronizing signal separated from a video signal by a counter circuit, correcting the pulse width, and eliminating an erroneous synchronizing signal. CONSTITUTION:The leading edge of the synchronizing signal S2 separated at a synchronizing separator circuit 20 is detected by an FF41, and a counter circuit 42 starts count up. At this time, when the synchronizing signal S2 is the erroneous synchronizing signal, the synchronizing signal S2 falls before the counted value of the counter circuit 42 arrives at (t1), therefore, the output of an OR circuit 46 goes to an L, and the counter circuit 42 starts count down. When the counted value of the counter circuit 42 arrives at (t2) in the count down, the output of an AND circuit 43 goes to the L, then, the counter circuit 42 is cleared. As a result, an output signal stays at the L, and no errorneous synchronizing signal is outputted. Also, the pulse width of the synchronizing signal is corrected at a constant value (t2-t1), then it is outputted.
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