发明名称 TEST SYSTEM FOR INTEGRATED CIRCUIT
摘要 PURPOSE:To take a test at a speed nearly as fast as in actual use by providing a storage circuit which stores test data and output data of a function circuit in an LSI to be tested. CONSTITUTION:A 1st switching circuit 2 is operated to connect the output of a shift register 1 so that the function circuit 10 is short-circuited. Then while the test data is outputted from the shift register 1 to the function circuit 10 successively, the output data from the function circuit 10 is stored at the tail of the queue in the shift register 1 successively. At this time, the function circuit 10 is operated at a specific operating speed to obtain the output data and a 2nd switching circuit 3 is operated after all output data are stored to make a connection so that the data stored in the shift register 1 are outputted. Lastly, the output data of the function circuit 10 stored in the shift register 1 are read out at the speed of the ability of an LSI tester to decide whether or not the function circuit 10 is normal.
申请公布号 JPS63153482(A) 申请公布日期 1988.06.25
申请号 JP19860301950 申请日期 1986.12.17
申请人 PFU LTD 发明人 NAKA KENICHI
分类号 G01R31/28;H01L21/822;H01L27/04 主分类号 G01R31/28
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