| 摘要 |
PURPOSE:To improve the freedom in the design of a logical gate by providing power wirings adjacent to fundamental cells. CONSTITUTION:In a C-MOS array, numerous fundamental rows 3, which respectively consist of numerous fundamental cells 2, are provided in parallel to each other on the central part of a semiconductor chip 1. The regions among these cell rows 3 are each used as a wiring channel. Main line power wirings 4a and 4b are provided on the peripheries of these cell rows 3. The wiring 4a of these constitutes a wiring for feeding a power potential VDD to the cells 2 and input/output buffer cells 7 and the wiring 4b constitutes a wiring for feeding an earth potential VSS to the cells 2 and the cells 7. Moreover, power wirings 6a and 6b for feeding a power source to the cells 2 are provided in such a way as to pass through the center, for example, of a cell row 3. Hereby, as the connection of gate electrodes on the cells 2 to the power wirings and the connection of feeding contacts to the power wirings can be performbd, outside of the cells, the disposal of floating, pins and the feeding contact can be easily performed. |
