发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 PURPOSE:To realize reduction and expansion of a pit aggregate, by nullifying a part of cell at the time of rearranging the cell by an arranging means. CONSTITUTION:A memory cell is divided into memory cell blocks of (n rows Xm columns) and a row selecting means RD at the memory cell block and a column selecting means CD at the memory cell block are provided commonly respectively. Also, a first switching means RSW supplies a row address AR or a row address AR+1 adjacent to the low address on each row selecting means, and a second switching means CSW supplies a column address AC or the column address AC+1 adjacent to the column address on each column selecting means. And the arranging means rearranges the (n X m)-number of cells of each memory cell block accessed by each row and column selection means. Therefore, it is possible to perform the access of a desired rectangular shape pit aggregate. In such a way, it is possible to easily perform the reduction and the expansion of the shape of the pit aggregate being accessed.
申请公布号 JPS63152092(A) 申请公布日期 1988.06.24
申请号 JP19860297629 申请日期 1986.12.16
申请人 FUJITSU LTD 发明人 OGAWA JUNJI
分类号 G11C11/401;G06T1/60;G11C11/34 主分类号 G11C11/401
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