| 摘要 |
PURPOSE:To prevent a surge from intruding, by forming, on the same wafer, a surge absorber element connected between the gate and the cathode of a GTO device, and giving a difference between the impurity concentration of a P2 layer surround by P<+> resistors and that of the P2 layer in the peripheral part where an N5 layer is formed. CONSTITUTION:A GTO is constituted of a main GTO part 1 situated at the central part, and an amplification GTO part 2 and a surge absorber part 13 which are situated on both sides of the main GTO part. Namely, P1 and P2 layers having a surface impurity concentration of 2X10<17> are formed by diffusing Ga into an N1 substrate having an impurity concentration of 4X10<13>, and an N5 layer having a surface concentration of 10<18> is formed by diffusing phosphorus into the P2 layer. Then, a P<+> buried gate whose impurity concentration is larger than 10<19> is arranged by diffusing boron into the P2 layer, and a P<+>2 layer having an impurity concentration of 10<18> is formed by diffusing and driving boron of low concentration into the P2 layer surrounded by the gate. On the P2 layer, a P<->2 layer is grown by epitaxy, but, in this process, the P<->2n layer is prevented form growing on a part of the N5 layer surface. Thereby, the intercepting capability is increased, and the surge intruding from wiring can be prevented.
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