| 摘要 |
According to the invention, an up/down counter (4) is in each case set to counting up with the rising edge (An) of the input voltage (Ue), as a result of which a first control signal (US1) is generated by means of an OR gate (6), the inputs of which are in each case logically combined with the outputs of the up/down counter (4), and a second channel (16) of an enable circuit (2) is blocked and its first channel (14) is activated, as a result of which a clock signal (Uc) is present at the clock input (22) of the up/down counter (4), that when a coded count is reached, a second control signal (US2) is generated as a result of which clock signal (Uc) is suppressed in the first channel (14) and a flip-flop (10) is set, that in each case the first channel (14) is blocked, the up/down counter (4) is set to counting down, the second control signal (US2) is set to zero and the second channel (16) is activated with the falling edge (Ab) of the input voltage (Ue), as a result of which the clock signal (Uc) is present at the clock input (22), and that when the count of zero is reached, the first control signal (US1) is set to zero, as a result of which the clock signal (Uc) is suppressed in the second channel (16) and the flip-flop (10) is reset. This provides an arbitrarily phase-shifted squarewave output voltage (Ua) from a squarewave input voltage (Ue). <IMAGE>
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