| 摘要 |
PURPOSE:To attain high speed operation by adopting the frequency synthesizer constitution including an equalized pulse rejection circuit controlled by an F/V converter so as to apply accurate N multiple to an inputted horizontal synchronizing signal. CONSTITUTION:An N multiple circuit 16 consists an equalizing pulse elimination circuit 40 consisting of an F/V converter 42 and a monostable multivibrator and a frequency synthesizer 100 whose frequency division ratio of frequency is set programmably. Since an output signal of the converter 42 is given to a time constant control terminal T of the circuit 40, even if the period of the horizontal synchronizing frequency included in the inputted composite synchronizing signal HD differs, the equalizing pulse is eliminated. Since the control of the time constant of the circuit 40 is subjected to feedforward by the converter 42, the circuit is operated at a high speed stably. The horizontal synchronizing signal output of the circuit 40 is given to a reference input terminal phi1 of the phase comparator 44 in the synthesizer 100 and the signal being N multiple of the frequency of said signal is led out by a 1/N frequency divider 60 preset with the frequency divider ratio N corresponding to the synchronizing signal of various devices used for an LPF 46 and a VCO 48. The multiple signal is synchronized accurately to the input signal by the synthesizer 100.
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