发明名称 HORIZONTAL TIMING SIGNAL GENERATING CIRCUIT
摘要 PURPOSE:To generate a stable horizontal timing signal by reducing noise components by the functions of a comparison means to compare the output of an A/D conversion means with a prescribed reference value, and of a noise reduction means provided in the preceding or following stage of said comparison means, and making the comparing out of the comparison means scarcely variable. CONSTITUTION:A television signal digitized by the A/D converter circuit 23 is supplied to the non-cyclic type noise reduction circuit 24, and the average amplitude of noise components is attenuated down to 1/n<1/2>. Then the television signal is supplied to a slicing circuit 28, and its level is compared with the slice level equivalent to the 1/4 of that of a horizontal synchronizing signal, and thus a slice signal is generated. In this case, since the noise components of the television signal are attenuated by the circuit 24, the flucture of the trailing edge of a slice signal is extremely little. In such a way, the fluctuation of the trailing edge of a slice signal influenced by noise components caused by the degrading of S/N can sufficiently blocked, and as a result, a stable horizontal timing signal can be obtained.
申请公布号 JPS63151284(A) 申请公布日期 1988.06.23
申请号 JP19860297607 申请日期 1986.12.16
申请人 TOSHIBA CORP 发明人 OI SHINICHI;YAMADA MASAHIRO
分类号 H04N5/06;H04N7/167;H04N7/169 主分类号 H04N5/06
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