发明名称 PARALLEL SIMPLIFYING SYSTEM FOR LOGICAL EXPRESSION
摘要 PURPOSE:To make a logical expression, processed by one computer, small, and to speed up a processing by dividing the sum of product type logical expression into 3<k> pieces, and at the same time, simplifying it by a parallel commutation, and merging the logical expression, simplified by the respective computer, K times. CONSTITUTION:Regarding the logical expression, in which pieces of variables exist, an operation to classify the said logical expression into three cases, i.e., the logical expression including the variable Xi, the logical expression including the inverse of Xi and the logical expression including neither Xi nor the inverse of Xi, is repeated K times, and 3<k> pieces of the logical expressions are formed, and each of them is assigned to the respective processor 21 of a parallel computer system, which has a communicating function between each other and is connected in a lattice shape. The respective processor 21 executes independently the simplifying processing of the logical expression for the given logical expression, and while it removes a redundant term by obtaining an information from the neiboring processor 21, it executes the merge processing of the simplified result. The merged result is set in the specified processor 21 corresponding to the respective merging step, and after the merge of K times, the simplified logical expression, corresponds to the original logical expression, is obtained.
申请公布号 JPS63149767(A) 申请公布日期 1988.06.22
申请号 JP19860298033 申请日期 1986.12.15
申请人 FUJITSU LTD 发明人 FUJITA MASAHIRO;NAKAJIMA ATSUKO
分类号 G06F9/44;G06F15/16;G06F15/80;G06F17/50 主分类号 G06F9/44
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