发明名称 DEBUGGING DEVICE
摘要 PURPOSE:To improve the reliability of debugging by mounting a memory corresponding to respective addresses of a mounted memory, addressing the memory in parallel with the mounted memory and displaying a writing miss of a program. CONSTITUTION:A bit map memory 4 in the debugging device B has a memory space completely corresponding to the mounted memory 2 and includes a one- bit data area. A multiplexer 6 switches access by the CPU5 or addressing parallel with the memory 2 by an address signal from the mounted CPU1. At the time of debugging in the run mode of the mounted CPU1, the memory 4 is addressed by the CPU1 simultaneously with the mounted memory 2. If data are to be written in the mounted memory 2 when the output of the memory 4 is in write inhibition similar to the mounted memory 2, an FF9 is set up, the output is inverted 10 to inhibit INH the writing and the output of the inverter 11 drives a light emitting diode 12. Thus, the writing miss of debugging can be easily prevented.
申请公布号 JPS59148959(A) 申请公布日期 1984.08.25
申请号 JP19830022412 申请日期 1983.02.14
申请人 TATEISHI DENKI KK 发明人 TAKAGI HARUO
分类号 G06F11/28;G06F11/36 主分类号 G06F11/28
代理机构 代理人
主权项
地址