| 摘要 |
PURPOSE:To obtain much decoding time by applying decoding simultaneously when a reproducing signal is being written and inhibiting the write of a reproduction signal to a memory area where the decoding is finished already through the result of comparison of an address comparison circuit. CONSTITUTION:A write address generating circuit 130 generating an address to write a reproducing signal, a decoding address generating circuit 13 to generate an address for decoding and an address comparison circuit 132 comparing two address outputted from the address generating circuit are provided. Then decoding is applied simultaneously while a reproducing signal is being written in a memory 121 and the address comparison circuit 132 decides whether or not the area is finished for the decoding of the write address inputted from the write address generating circuit 130 and in the case the area into which the decoding is finished, the write of the reproducing signal is inhibited. Thus, the time used for decoding is not limited for the period without the reproducing signal.
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