发明名称 REFRESH CONTROL SYSTEM
摘要 PURPOSE:To suppress a current required for refreshing a dynamic memory to a low value by deirding a memory into plural blocks and sequentially refreshing respective with shifting a time. CONSTITUTION:A control part 10 is connected with plural memory blocks 1, 2...n through a bus 15 and is connected with various adapters 17 such as a disk control part, a line control part and the like. A memory refresh request signal from the control part 10 is firstly inputted to the memory block 1 through a refresh request signal line 16, and the memory block 1 is refreshed. The memory block 1 outputs the refresh signal to the memory block 2 which has been refreshed. The fresh memory 2 receives the refresh request signal and refreshes itself. Thus, memory blocks 3, 4... sequentially execute refreshing. Consequently, the capacity of power source required is reduced, whereby total cost is reduced.
申请公布号 JPS63148492(A) 申请公布日期 1988.06.21
申请号 JP19860294146 申请日期 1986.12.10
申请人 FUJITSU LTD 发明人 NISHIMURA NAOYUKI;HASHIMOTO SHIGERU
分类号 G11C11/406;G11C11/34 主分类号 G11C11/406
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