| 摘要 |
PURPOSE:To efficiently access a dynamic RAM (DRAM) in a minimum waiting time by automatically burst-refreshing the DRAM and shifting a system to a CPU mode just after a DMAC (direct memory access controller) has terminated a memory access. CONSTITUTION:If an address to which the direct memory access controller distributed by an address distribution means accesses is stored in an address storage a means, and if a first refresh address designation means designates a refresh address while collating to the address stored in the address storage means, the first refresh means refreshes the dynamic RAMs 4a-4d. A second refresh means burs-refreshes the dynamic RAMs 4a-4d when refreshing terminates and just before the system shifts to the CPU mode. Thus, a refreshing action at the time of switching respective modes can be simplified, and parallel parallel processings can be attained without the processing capacity of the CPU.
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