| 摘要 |
PURPOSE:To improve the use efficiency of a bus to increase the processing speed of a system by stopping to prefetch instructions from a queue register when it is detected that a specific instruction is stored in the queue register. CONSTITUTION:Instructions are fetched from an instruction storage part 1 to a queue register 3 through a bus 8 and instructions are transferred to an instruction executing part 4 in the order of fetching. In this stream, a decoder 10 always decodes a decode information signal 12 to monitor instructions fetched in the queue register 3. If a branch instruction is fetched, the decoder 10 reports it to a bus control part 5A by a detection signal 13. The bus control part 5A stops the following fetch operation by a control circuit 11. When the branch instruction is executed by the instruction executing part 4 thereafter, the bus control part 5A starts fetching on the basis of the branch address.
|
