发明名称 POWER SUPPLY CONTROL SYSTEM
摘要 <p>PURPOSE:To shorten the time loss from power-off to remaking of a power supply for a computer system by setting the environment latency time to a required minimum in accordance with prevailing conditions for each time. CONSTITUTION:A time setting part 32 and a timer 33 are incorporated in a power supply controller 3. The shortest environment latency time required for satisfaction of conditions to remake the power source of the computer system is obtained and is set to the time setting part 32. Meanwhile, a program which reads out the latency time set to the time setting part 32 and sets it to the timer 33 is built in a test program 21 of a storage device 2. A host processor 1 causes a control part 31 of the power supply controller 3 to execute this program and turns off power sources of the storage device 2 and the host processor 1 itself. When the latency time set to the timer 33 elapses, the timer 33 outputs the signal reporting this expiration to the control part 31 to make power sources of the host processor 1 and the storage device 2.</p>
申请公布号 JPS63148317(A) 申请公布日期 1988.06.21
申请号 JP19860296424 申请日期 1986.12.12
申请人 NEC CORP 发明人 YAMAMOTO YOSHINORI
分类号 G06F1/26;G06F1/00;H02J1/00 主分类号 G06F1/26
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