| 摘要 |
PURPOSE:To improve the data transfer capability of a bus to improve the system performance by preparing two busses for a system to separate the data transfer to a memory control part and the data transfer from the memory control part to another unit in the system from each other. CONSTITUTION:A write bus 1 through which an active unit group transfers the memory read/write address and memory write data to a storage control unit 7 and a read bus 2 through which the storage control unit 7 transfers the result of the requested memory operation to a request source unit are provided as two common busses controlled independently of each other. The use efficiency of busses is improved in comparison with a system using one common bus to improve the data transfer capability. Plural central processing units 3 can be added to the system by this pipeline operation to realize the system of high performance.
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