VARIABLE WORK LENGTH SHIFT REGISTER

摘要

PURPOSE:To extremely decrease power consumption by providing a read address decoder which gives a sequential access to a memory cell with read signal produced from a write timing signal and a bit length selecting signal. CONSTITUTION:A read timing signal generating circuit 2 produces a read timing signal RT later than a write timing signal WT by a prescribed time from the bit length setting input signals a1-an. Thus a read address decoder 4 works. The input data DI are successively written into the memory cells designated by a write address decoder 3 which is controlled by the signal WT. Then the data DI are read successively out of the memory cells designated by the decoder 4 which is controlled by the signal RT produced by the circuit 2. Thus the output data DO is obtained. In such a way, the power consumption is extremely reduced since just a part of an entire circuit works even in the action.