| 摘要 |
A bus control system in a multiple-processor system constituted by connecting, via address and data buses (51, 52, 53), modules (1, 2) that contain devices such as processors (15, 25) and input/output devices. The modules (1, 2) are equipped with bus arbitration control circuits (14, 24), and two-way bus switches (11, 12, 13; 21, 22, 23). The bus control system is further equipped with control signal lines (61, 62, 63) for bus arbitration connecting the bus arbitration control circuits (14, 24). The two-way bus switches are opened and closed under the control of the bus arbitration control circuits and, as a result, the processors are connected in parallel or through pipelines. |
