发明名称 ENHANCED DENSITY MODIFIED ISOPLANAR PROCESS
摘要 An improved process for fabricating modified isoplanar integrated circuits with enhanced density incorporates a number of interactive and co-acting process steps. First, oxide isolation of epitaxial islands is effected in a two step process, forming a thin thermally grown oxide layer (32), over the surfaces of shallow trenches and then filling the shallow trenches with deposited low temperature oxide (34). Second, an enhanced single polycrystalline or polysilicon layer process uses a blanket implant, eliminates certain masking and etching steps, and defines the polycrystalline layer. Third, a new method and structure is provided for dielectrically isolating and separating contact locations on different surface levels of the integrated circuit structure adjacent to step locations between the surface levels. Finally, a new method constitutes all of the electrical contact locations for the elements of the integrated circuit structure at the same substantially isoplanar level.
申请公布号 WO8804473(A1) 申请公布日期 1988.06.16
申请号 WO1987US03276 申请日期 1987.12.10
申请人 FAIRCHILD SEMICONDUCTOR CORPORATION 发明人 DESBIENS, DONALD, J.;ELDRIDGE, JOHN, W.;HOWELL, PAUL, J.
分类号 H01L29/73;B01J3/00;B29C67/24;C08G63/60;C08J5/04;C08L67/00;F04B37/14;H01L21/02;H01L21/285;H01L21/331;H01L21/60;H01L21/76;H01L21/762;H01L21/768;H01L21/822;H01L21/8222;H01L23/522;H01L27/04;H01L27/06;(IPC1-7):H01L21/94;H01L21/44 主分类号 H01L29/73
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