| 摘要 |
PURPOSE:To facilitate the generation of data and to accurately allow a timing signal to coincide with the time of logic simulator output data by controlling a FF with the outputs of fine delay parts which is obtained by delaying timing signals from respective memories. CONSTITUTION:Timing information and counting information to be generated are stored in memories 23, 24, and 25 corresponding to the counting result of a reference signal counting part 22 which counts a reference signal from a reference signal generation part 21. The timing signals outputted from the memories 23 and 24 are delayed by fine delay parts 41 and 42 according to delay information read out of a memory. The FF 49 is set and reset with the outputs of the fine delay parts 41 and 42 and the output of the FF 49 is supplied as a test signal to the logic circuit to be tested. Then when the counted value of the counting part 22 reaches the stored timing of the memory 25, the delay information is read out of the memory 25 to output the timing signal, which is delayed by a fine delay part 43 and supplied to a comparator 51. here, it is decided through the comparator 51 whether the output of the circuit 14 has a prescribed logic level or not.
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