| 摘要 |
PURPOSE:To increase the maximum frequency division frequency by using a frequency divider consisting of two FF circuits and varying the duty ratio of ON/OFF time of the 1st and 2nd transistors (TRs) of a differential amplifiers by a different voltage so as to prolong the read time of data. CONSTITUTION:When the FF of the circuit 1 is in the data read mode, the base bias voltage of a TR 3 is slightly lower than the base bias voltage of a TR 4. Thus, even when the input signal is increased positively and the duty ratio exceeds 50%, the TR 3 is hardly turned on and it takes much time for the TR 3 to be turned on and in the latch mode. With the input signal decreased after in the latch mode once, the TR 3 is turned off before the duty ratio of the input signal reaches 50%, the TR 4 is turned on to form the data read mode. ON the other hand, the circuit block 2 reaches the opposite state as the case with the block 1, and when the input voltage is increased negatively, the read time is extended the same as the case with the FF of the block 1. Thus, the maximum frequency division is increased in both the cases.
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