发明名称 DATA TRANSFER CONTROL SYSTEM IN MULTIPROCESSOR SYSTEM
摘要 PURPOSE:To prevent the reduction of transfer capacity and the generation of a transfer stop state or the like by restricting the sending of a data packet when the difference between the count values of counting means indicates a value smaller than the contents of a block residual limiting register. CONSTITUTION:The titled system is provided with a counting means 17 for counting the number of data packets accumulated in the storage block of an input/output buffer 12 in a transfer control circuit (TC) 5 in each unit processor (UP) and waiting for being sent in each input/output terminal to be sent and a counting means 16 for counting the number of unused idle storage blocks. In addition, a block number ratio limiting register 18 or a block residual limiting number register 19 to be set up by a CP (processor for executing random processing under control based upon a program) 4 is prepared and always monitored by the CP 4 and an input/output control circuit 11. When the using rate of the input/output buffer 12 is increased, the sending of data packets is restricted. Consequently, excess data sending can be suppressed.
申请公布号 JPS63143661(A) 申请公布日期 1988.06.15
申请号 JP19860290053 申请日期 1986.12.05
申请人 FUJITSU LTD 发明人 IKESAKA MORIO;INOUE KOICHI
分类号 G06F15/16;G06F15/163;G06F15/177 主分类号 G06F15/16
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