| 摘要 |
<p>PURPOSE:To extend a data transfer effective period by using an output signal from a shift register as a gate input signal for a transfer gate transistor (TR) connected between an I/O bus and a data register. CONSTITUTION:Input/output buses I/O, the inverse of I/O, are precharged by a precharge signal PIO and an input signal from an external input terminal DIN is amplified by an amplifier AMP and led into the I/O buses I/O, the inverse of I/O, so that the I/O buses I/O, the inverse of I/O, are set up between high and low potential values or between low and high potential values to hold data. When a shift register output signal SROn is turned to high potential, transfer gate TRs T01, T02 are activated, the I/O buses I/O, the inverse of I/O, and a data register DR are connected and the data in the I/O buses are transferred to the data register DR. At that time, the data transfer effective period becomes t1 and respective signals SROn, PIO, I/O, the inverse of I/O constitute one cycle for two cycles of a reference signal because an interleaving format is used.</p> |
