| 摘要 |
<p>A dynamic semiconductor memory apparatus which can sense data at high speed includes first and second bit line pairs (BL, @BL; alpha , @), memory cells (C1, C2) connected to the first bit line pair (BL, @BL), barrier transistors (T1, T2), connected between the first and second bit line pairs (BL, @BL; alpha , @), its impedance being varied in accordance with a level of an input first control signal, and a control unit (15) for outputting the first control signal to the barrier transistors (T1, T2) and for controlling transmission of a potential difference generated in the first bit line pair (BL, @BL) due to data read out from the memory cells (C1, C2) to the second bit line pair ( alpha , @) in accordance with an input read control signal. The first control signal is at a first level for a first predetermined time interval after the read control signal is input, at a second level for a second predetermined time interval after the first predetermined time interval has passed, and at the first level after the second predetermined time interval has passed, and an impedance of the barrier transistors (T1, T2) obtained when the first control signal is at the first level is smaller than that obtained when the control signal is at the second level.</p> |
