| 摘要 |
PURPOSE:To complete a designing process in a short time by means of an automatic layout system by unifying the arranging sequence of signals at terminals of a bus signal at the upper side and the lower side of all the blocks as well as at the left side and the right side of all the blocks. CONSTITUTION:At all blocks where chips are divided according to their logic, the arranging sequence of terminals for a bus signal at the upper side and the lower side is unified and the arranging sequence at the left side and the right side is unified. When the terminals for the bus signal are located at the side of adjacent blocks, the sequence of a bundled wiring part 2 for the bus signal and the arranging sequence of the terminals for the bus signal are unified. By this method, a wiring process can be completed easily if perpendicular lines are drawn from signal terminals 31, 32...3n to the bundles wiring part 2 for the bus signal. The arranging sequence of the terminals for the bus signal at the upper side and the lower side of each block is designated as 31, 32...3n as counted from the left. In addition, the arranging sequence of the terminals for the bus signal at the left side and the right side of each block is designated as 31, 32...3n as counted from the top. The reversed arranging sequence is permissible as long as the arranging sequence for all the block is uniform.
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