发明名称 |
Bit line equalization in a memory |
摘要 |
A memory has a memory cells located at intersections of bit line pairs and word lines. During a write mode of the memory, the bit lines are at a maximum voltage separation. For a read to occur following a write, the bit lines must first be equalized. Because of the extent of the voltage separation during a write, equalizing the bit lines can cause a large peak current drain on the power supply. This peak current is reduced by partially charging the bit lines in response to a write to read transition then bringing the bit lines to the final equalization voltage in response to a transition of the row address. The partial charging is ensured of occurring first in the event that the write to read transition occurs simultaneously with a row address transition to ensure a reduced peak current.
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申请公布号 |
US4751680(A) |
申请公布日期 |
1988.06.14 |
申请号 |
US19860835681 |
申请日期 |
1986.03.03 |
申请人 |
MOTOROLA, INC. |
发明人 |
WANG, KARL L.;BADER, MARK D.;VOSS, PETER H. |
分类号 |
G11C11/41;G11C7/12;G11C11/419;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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