| 摘要 |
A semiconductor memory device comprising a plurality of bit lines and a plurality of dummy bit lines respectively associated with the bit lines, a plurality of memory cells arranged in association with each of the bit lines, a dummy cell arranged in association with each of the dummy bit lines, and a sense amplifier. The sense amplifier comprises a differential amplifier network responsive to a first activating signal for comparing the potential at one of the bit lines with the potential at the associated one of the dummy bit lines and producing one of two complementary signals selectively depending upon the relationship between the potentials compared, and a signal latch network responsive to a second activating signal and to each of the complementary signals output from the differential amplifier network the for producing one of two output signals respectively corresponding to the complementary signals from the differential amplifier means, the signal latch network being operative to have the aforesaid one of the output signals latched therein for a controlled period of time after the particular output signal has been produced by the signal latch network.
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