| 摘要 |
A multi-digit, mixed-base or mixed-radix counter of the type used in digital computing devices wherein the value of each digit of the counter is stored in two parts: a first part being the normal numerical value except in certain exceptional cases; and a second part which is zero except in the exceptional cases in which it is a binary one. The exceptional case is when the value to be represented by the counter digit is a terminal digit value, i.e., a maximum digit value when the counter is incrementing or zero value when the counter is decrementing. In the case of a decrementing counter where the normal terminal digit value is a zero, each zero value is replaced with the corresponding maximum digit value for that digit in the first part of the counter, but the second part of the counter identifies in which (if any) of the digits of the first part of the counter such a substitution has been made. This quick-acting counter experiences changes of one digit value at any counting state and can be used to generate sequences of addresses through the addition of successive increments wherein the proper increment is based on the state of only the second part of the counter.
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