| 摘要 |
PURPOSE:To increase pipeline processing speed by simultaneously performing the preceding execution processing and the succeeding address calculation if information used for execution of a preceding instruction and that for execution address calculation of a succeeding instruction coincide with each other. CONSTITUTION:A pipeline control area PC indicating whether contents of a register used for execution of an instruction to be subjected to execution processing are changed at the time of instruction execution or not is provided for this instruction, and the execution address of the succeeding instruction is calculated in parallel with execution of the preceding instruction. A comparator 7 compares Reg1 of the preceding instruction and Reg2 of the succeeding instruction with each other, and the result is supplied to a control circuit 13. The control circuit 13 supplies the command signal, which commands calculation of the execution address, to an execution address calculating part 9 based on the information of the area PC of the preceding instruction stored in a first instruction register 1 and the signal from the comparator 7.
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