| 摘要 |
PURPOSE:To simplify memory management and quickly transfer data by managing information bits of a mask register by a MPU. CONSTITUTION:A dual port memory circuit which can be arbitrarily accessed by processors MPUa and MPUb through two signal paths and has plural storage areas is provided with an occupation register R3 and a release register R4 which indicate the occupation and release of each storage area respectively, an interruption source register R2, and an interruption mask register R1. An interruption request signal is generated in accordance with corresponding information bits of the interruption source register R2 and the interruption mask register R1, and information bits of the interruption source register R1 which refer to an interruption mask signal are taken out correspondingly to this interruption request signal. |
