| 摘要 |
PURPOSE:To speedily write and read data to and from each memory cell and to shorten a testing time by simultaneously operating all plural blocks in each active cycle in a test mode. CONSTITUTION:A decoder circuit 10 constituted of 1st and 2nd circuits is provided. A driving signal outputted from a 1st decoder circuit is given to the sense amplifier of a memory cell array block corresponding to a row address RA8=1, while a driving signal obtained from a 2nd decoder circuit is given to the sense amplifier of a memory cell array block corresponding to a row address RA8=0. Thus, the sense amplifiers are activated in the test mode together with the blocks with the row addresses RA8=0 and RA8=1. Accordingly, all bits can be read out and written with a half of the number of cycles in a normal mode, thereby shortening the testing time.
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