| 摘要 |
PURPOSE:To prevent a latchup by increasing the resistance value of a power source wiring layer for supplying a potential to the source electrodes of a plurality of transistors larger than that of a power source wiring layer for supplying a substrate potential. CONSTITUTION:A P<+> type diffused layer is formed by doping on an N-type semiconductor substrate surface, a power source wiring layer 1 for supplying a source potential is formed, and P<+> type diffused layers 2a, 2b are formed on a P-type region surface formed on part of the N-type substrate. Then, N<+> type diffused layers 3a, 3b and N<+> type diffused layers 4a, 4b are formed on another region on the substrate. Thereafter, polycrystalline silicon layers 11a, 11b, 11c which becomes word lines are formed, and gate electrodes are formed in combination of 4 regions crossing on the layer 1 and the layers 4a, 4b, and 2 regions crossing on the layer 4a and the layer 4b. Subsequently, it is covered with a power source wiring layer 13, and the resistance value of the layer 13 is reduced smaller than that of the layer 1. Then, aluminum wirings are formed, and covered with ground wiring layers 14a, 14b, bit wiring layers 15a, 15b, and wiring layers 16a, 16b. Thus, a latchup can be prevented. |
