| 摘要 |
PURPOSE:To prevent the resistance of an operation layer of an FET from increasing by flash annealing the surface of the operation layer so as to activate an n<+> type layer in the state that the surface of the operation layer is covered with high-melting point metal. CONSTITUTION:With a resist mask 105 on an Au layer 104 formed on an operation layer 102 as a mask the layer 104 is anisotropically etched to form an Au layer 11. Then, the mask 105 is removed, the exposed surfaces of a WN layer 103 and the layer 11 are covered with an SiO2 layer, anisotropically etched to form a sidewall layer 12 on the layer 11. With the layers 11, 12 as masks the layer 103 is etched to form a WN layer 13, and an N<+> type layer 14 is formed by implanting Si<+> ions. Then, after the layer 12 is removed, the whole surface of a GaAs substrate is covered with a PSG layer 16, and flash annealed to activate the layer 14. After the layer 16 is separated on the whole surface with NH4F solution, with the layer 11 as a mask the layer 13 is anisotropically etched to form a short gate electrode 15. Then, an AuGe/Pt layer is covered on the layer 14 to provide a source electrode 17S and a drain electrode 17D. Thus, the resistance of the operation layer is stably held up to 850 deg.C of heat treating temperature, thereby reducing the n<+> type layer resistance.
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