| 摘要 |
PURPOSE:To accelerate arithmetic calculation without expanding a circuit scale so large, by dividing an input data into high-order bits and low-order bits, and performing the addition processing on them respectively. CONSTITUTION:The input data of n-bits is divided into the low-order (n-m)-bits and the high-order m-bits by a division means 13. And a first addition means 14 performs addition on the low-order (n-m)-bits and sends an arithmetic result to a data holding means 15 which holds the high-order m-bits, and also, starts another arithmetic calculation. Meanwhile, a second addition means 16 performs the addition of the m-bits by using the output of the means 15, and arranges an obtained arithmetic result and the arithmetic result of the first addition means 14 at an addition result combining means 17, then, the arithmetic result of n-bits can be obtained. In such way, it is possible to accelerate the arithmetic calculation without expanding the circuit scale so large.
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